View CY62157DV3010_5034352.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

8-Mbit (512K x 16) MoBL Static RAM
Features
CY62157DV30 MoBL(R)
Temperature ranges Industrial: -40 C to 85 C Very high speed: 55 ns Wide voltage range: 2.20 V-3.60 V Pin-compatible with CY62157CV25, CY62157CV30, and CY62157CV33 Ultra-low active power Typical active current: 1.5 mA @ f = 1 MHz Typical active current: 12 mA @ f = fmax Ultra-low standby power Easy memory expansion with CE1, CE2, and OE features Automatic power-down when deselected Complementary metal oxide semiconductor (CMOS) for optimum speed/power Available in Pb-free and non Pb-free 48-ball fine ball grid array (FBGA), and Pb-free 44-pin thin small outline package (TSOPII) package

This is ideal for providing More Battery Life (MoBL(R)) in portable applications such as cellular telephones.The device also has an automatic power-down feature that significantly reduces power consumption. The device can also be put into standby mode when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE1HIGH or CE2 LOW), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE1 LOW, CE2 HIGH and WE LOW). Writing to the device is accomplished by taking Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A18). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table for a complete description of read and write modes. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.

Functional Description
The CY62157DV30 is a high-performance CMOS static RAM organized as 512K words by 16 bits. This device features advanced circuit design to provide ultra-low active current.
Logic Block Diagram
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER
DATA-IN DRIVERS
512K x 16 RAM Array
SENSE AMPS
I/O0-I/O7 I/O8-I/O15
COLUMN DECODER
BHE WE OE BLE
A11 A12 A13 A14 A15 A16 A17 A18
CE2
CE1
Power-down Circuit
Cypress Semiconductor Corporation Document #: 38-05392 Rev. *J
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised October 25, 2010
[+] Feedback
CY62157DV30 MoBL(R)
Contents
Product Portfolio .............................................................. 3 Pin Configuration .............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 4 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 5 Data Retention Waveform................................................. 5 Switching Waveforms ...................................................... 7 Truth Table ...................................................................... 10 Ordering Information ...................................................... 11 Ordering Code Definition ........................................... 11 Package Diagram ............................................................ 12 Acronyms ........................................................................ 13 Document Conventions ................................................. 13 Units of Measure ....................................................... 13 Document History Page ................................................. 14 Sales, Solutions, and Legal Information ...................... 15 Worldwide Sales and Design Support ....................... 15 Products .................................................................... 15 PSoC Solutions ......................................................... 15
Document #: 38-05392 Rev. *J
Page 2 of 15
[+] Feedback
CY62157DV30 MoBL(R)
Product Portfolio
Power Dissipation Product Range VCC Range (V) Min CY62157DV30LL Industrial 2.2 Typ[1] 3.0 Max 3.6 55, 70 Speed (ns) Operating ICC, (mA) f = 1MHz Typ[1] 1.5 Max 3 f = fmax Typ[1] 12 Max 15 Standby ISB2, (A) Typ[1] 2 Max 8
Pin Configuration[2, 3, 4]
1 BLE I/O8 I/O9 VSS VCC 2 OE BHE I/O10 I/O11 3 A0 A3 A5 A17 4
48-Ball FBGA Pinout
Top View
5 A2 CE1 I/O1 I/O3 I/O4 I/O5 WE A11 6 CE2 I/O0 I/O2 Vcc Vss I/O6 I/O7 NC A B C D E F G H
44-pin TSOP II Pinout
Top View
A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A18 A17 A16 A15 A14
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
A1 A4 A6 A7 A16 A15 A13 A10
I/O12 DNU A14 A12 A9
I/O14 I/O13 I/O15 A18 NC A8
A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 A8 A9 A10 A11 A12 A13
Notes 1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25 C. 2. NC pins are not internally connected on the die. 3. DNU pins have to be left floating. 4. The 44-TSOPII package device has only one chip enable pin (CE).
Document #: 38-05392 Rev. *J
Page 3 of 15
[+] Feedback
CY62157DV30 MoBL(R)
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature ............................... -65 C to + 150 C Ambient temperature with power applied .......................................... -55 C to + 125 C Supply voltage to ground potential .......................................... -0.3 V to VCC(max) + 0.3 V DC voltage applied to outputs in High-Z State[5, 6] ......................... -0.3 V to VCC(max) + 0.3 V DC input voltage[5, 6] ....................... -0.3 V to VCC(max) + 0.3 V
Output current into outputs (LOW) .............................. 20 mA Static discharge voltage........................................... >2001 V (per MIL-STD-883, Method 3015) Latch-up current ...................................................... >200 mA
Operating Range
Device CY62157DV30LL Range Industrial Ambient Temperature (TA) -40 C to +85 C VCC[7] 2.20 V to 3.60 V
Electrical Characteristics Over the Operating Range
Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 Description Output HIGH voltage Output LOW voltage Input HIGH voltage IOH = -0.1 mA IOH = -1.0 mA IOL = 0.1 mA IOL = 2.1 mA VCC = 2.2 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 2.7 V to 3.6 V Input leakage current Output leakage current VCC Operating supply current Automatic Power-down current -- CMOS inputs Automatic Power-down current -CMOS inputs GND < VI < VCC GND < VO < VCC, Output disabled f = fMAX = 1/tRC f = 1 MHz CE1 > VCC 0.2 V or CE2 < 0.2 V or (BHE and BLE) > VCC 0.2 V, VIN > VCC - 0.2 V, VIN < 0.2 V f = fMAX (Address and Data Only), f = 0 (OE, WE), VCC = 3.60V CE1 > VCC- 0.2 V or CE2 < 0.2 V, (BHE and BLE) > VCC 0.2 V, VIN > VCC - 0.2 V or VIN < 0.2 V, f = 0, VCC = 3.60 V Ind'l Ind'l VCC = VCCmax LL IOUT = 0 mA LL CMOS levels Ind'l LL Test Conditions VCC = 2.20 V VCC = 2.70 V VCC = 2.20 V VCC = 2.70 V -55 Min 2.0 2.4 - - 1.8 2.2 -0.3 -0.3 -1 -1 - Typ[8] - - - - - - - - - - 12 1.5 - 2 Max - - 0.4 0.4 VCC + 0.3 VCC + 0.3 0.6 0.8 +1 +1 15 3 8 Unit V V V V V V V V A A mA mA A
Input LOW voltage VCC = 2.2 V to 2.7 V
ISB2
Ind'l
LL
-
2
8
A
Capacitance
Parameter[9, 10] CIN COUT Description Input capacitance Output capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = VCC(typ) Max 10 10 Unit pF pF
Notes 5. VIL(min.) = -2.0 V for pulse durations less than 20 ns. 6. VIH(max)= VCC+0.75 V for pulse duration less than 20 ns. 7. Full device AC operation assumes a 100 s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization. 8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 C 9. Tested initially and after any design or process changes that may affect these parameters. 10. The input capacitance on the CE2 pin of the FBGA package and on the BHE pin of the 44TSOPII package is 15 pF.
Document #: 38-05392 Rev. *J
Page 4 of 15
[+] Feedback
CY62157DV30 MoBL(R)
Thermal Resistance
Parameter[11] JA JC Description Thermal resistance (Junction to ambient) Thermal resistance (Junction to case) Test Conditions Still air, soldered on a 3 x 4.5 inch, four-layer printed circuit board FBGA 39.3 9.69 TSOP II 35.62 9.13 Unit C / W C / W
AC Test Loads and Waveforms
VCC OUTPUT
30 pF / 50 pF
R1
VCC GND R2 10%
ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns
Rise Time = 1 V/ns
INCLUDING JIG AND SCOPE
Equivalent to: THEVENIN EQUIVALENT RTH OUTPUT V 2.50 V 16667 15385 8000 1.20 3.0 V 1103 1554 645 1.75 Unit V
Parameters R1 R2 RTH VTH
Data Retention Characteristics (Over the Operating Range)
Parameter VDR ICCDR Description VCC for data retention Data retention current VCC= 1.5 V CE1 > VCC - 0.2 V or CE2 < 0.2 V or (BHE and BLE) > VCC 0.2 V, VIN > VCC - 0.2 V or VIN < 0.2 V Ind'l Conditions Min 1.5 - Typ[12] - - Max - 4 Unit V A
tCDR[11] tR[13]
Chip deselect to data retention time Operation recovery time
0 55
- -
- -
ns ns
Data Retention Waveform[14]
VCC
CE1 or BHE.BLE
VCC, min. tCDR
DATA RETENTION MODE VDR > 1.5 V
VCC, min. tR
or CE2
Notes 11. Tested initially and after any design or process changes that may affect these parameters 12. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 C 13. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 100 s or stable at VCC(min.) > 100 s. 14. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
Document #: 38-05392 Rev. *J
Page 5 of 15
[+] Feedback
CY62157DV30 MoBL(R)
Switching Characteristics Over the Operating Range
Parameter[15] Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write Cycle[18] tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE Write cycle time CE1 LOW and CE2 HIGH to write end Address set-up to write end Address hold from write end Address set-up to write start WE pulse width BLE/BHE LOW to write end Data set-up to write end Data hold from write end WE LOW to High-Z
[16, 17] [16]
Description
55 ns Min 55 - 10 - - 5 - 10 - 0 - - 10 - 55 40 40 0 0 40 40 25 0 - 10 Max - 55 - 55 25 - 20 - 20 - 55 55 - 20 - - - - - - - - - 20 -
Unit
Read cycle time Address to data valid Data hold from address change CE1 LOW and CE2 HIGH to data valid OE LOW to data valid OE LOW to LOW Z
[16]
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
OE HIGH to High Z[16, 17] CE1 LOW and CE2 HIGH to Low Z[16] CE1 HIGH and CE2 LOW to High Z
[16, 17]
CE1 LOW and CE2 HIGH to Power-up CE1 HIGH and CE2 LOW to Power-down BLE/BHE LOW to data valid BLE/BHE LOW to Low Z
[16] [16, 17]
BLE/BHE HIGH to HIGH Z
WE HIGH to Low-Z
Notes 15. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH as shown in the "AC Test Loads and Waveforms" section. 16. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 17. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state. 18. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.
Document #: 38-05392 Rev. *J
Page 6 of 15
[+] Feedback
CY62157DV30 MoBL(R)
Switching Waveforms
Figure 1. Read Cycle 1 (Address Transition Controlled)[19, 20] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Figure 2. Read Cycle 2 (OE Controlled)[20, 21]
ADDRESS tRC CE1 CE2 BHE/BLE tDBE tHZBE tPD tHZCE tACE
tLZBE OE
DATA OUT
tDOE tLZOE HIGH IMPEDANCE tLZCE tPU
tHZOE HIGH IMPEDANCE ICC ISB
DATA VALID
SUPPLY CURRENT
50%
50%
Notes 19. The device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. 20. WE is HIGH for read cycle. 21. Address valid prior to or coincident with CE1, BHE, BLE transition LOW and CE2 transition HIGH.
Document #: 38-05392 Rev. *J
Page 7 of 15
[+] Feedback
CY62157DV30 MoBL(R)
Switching Waveforms (continued)
Figure 3. Write Cycle 1 (WE Controlled)[22, 23, 24] tWC ADDRESS tSCE CE1 CE2 tAW tSA WE tBW tPWE tHA
BHE/BLE
OE tSD DATA I/O
See note 25
tHD
VALID DATA tHZOE Figure 4. Write Cycle 2 (CE1 or CE2 Controlled)[22, 23, 24]
tWC
ADDRESS tSCE CE1 CE2 tSA tAW tPWE WE tBW tHA
BHE/BLE
OE tSD DATA I/O
See note 25
tHD
VALID DATA tHZOE
Notes 22. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write 23. Data I/O is high-impedance if OE = VIH. 24. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high-impedance state. 25. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05392 Rev. *J
Page 8 of 15
[+] Feedback
CY62157DV30 MoBL(R)
Switching Waveforms (continued)
Figure 5. Write Cycle 3 (WE Controlled, OE LOW)[26] tWC ADDRESS tSCE CE1 CE2
BHE/BLE
tBW tAW tSA tPWE tHA
WE tSD DATA I/O
See note 27
tHD
VALID DATA tHZWE Figure 6. Write Cycle 4 (BHE/BLE Controlled, OE LOW)[26] tWC tLZWE
ADDRESS CE1 CE2
tSCE tAW tHA tBW tSA
BHE/BLE
WE
tPWE tSD tHD
DATA I/O
See note 27
VALID DATA
Notes 26. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high-impedance state 27. During this period, the I/Os are in output state and input signals should not be applied
Document #: 38-05392 Rev. *J
Page 9 of 15
[+] Feedback
CY62157DV30 MoBL(R)
Truth Table
CE1 H X X L L L L L L L L L CE2 X L X H H H H H H H H H WE X X X H H H H H H L L L OE X X X L L L H H H X X X BHE X X H L H L L H L L H L BLE X X H L L H H L L L L H Inputs/Outputs High Z High Z High Z Data out (I/O0-I/O15) Data out (I/O0-I/O7); High Z (I/O8-I/O15) High Z (I/O0-I/O7); Data out (I/O8-I/O15) High Z High Z High Z Data in (I/O0-I/O15) Data in (I/O0-I/O7); High Z (I/O8-I/O15) High Z (I/O0-I/O7); Data in (I/O8-I/O15) Mode Deselect/Power-down Deselect/Power-down Deselect/Power-down Read (upper byte and Lower byte) Read (lower byte only) Read (upper byte only) Output disabled Output disabled Output disabled Write (upper byte and Lower byte) Write (lower byte only) Write (upper byte only) Power Standby (ISB) Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Document #: 38-05392 Rev. *J
Page 10 of 15
[+] Feedback
CY62157DV30 MoBL(R)
Ordering Information
Speed (ns) 55 Ordering Code CY62157DV30LL-55BVI CY62157DV30LL-55BVXI CY62157DV30LL-55ZSXI Package Diagram 51-85150 51-85087 Package Type 48-ball (6 x 8 x 1 mm) FBGA 48-ball (6 x 8 x 1 mm) FBGA (Pb-free) 44-pin TSOP II (Pb-free) Operating Range Industrial
Ordering Code Definition
CY V30 LL 55 XXX X
Tem perature Grade I = Industrial Package Type : ZSX : TSOP II (Pb-free) BVX : VFBGA (Pb-free) BV : VFBGA Speed Grade Low Power Voltage = 3.0 Bus W idth = X16 D = 130nm Technology Density = 8M bit M oBL SRAM Fam ily Com pany ID: CY = Cypress
621
5
7D
Document #: 38-05392 Rev. *J
Page 11 of 15
[+] Feedback
CY62157DV30 MoBL(R)
Package Diagram
Figure 7. 48-Pin VFBGA (51-85150)
51-85150 *F
Figure 8. 44-pin TSOP II (51-85087)
51-85087 *C
Document #: 38-05392 Rev. *J
Page 12 of 15
[+] Feedback
CY62157DV30 MoBL(R)
Acronyms
Acronym CMOS I/O SRAM VFBGA TSOP input/output static random access memory very fine ball grid array thin small outline package Description complementary metal oxide semiconductor
Document Conventions
Units of Measure
Symbol C A mA MHz ns pF V W Unit of Measure degrees Celsius microamperes milliampere megahertz nanoseconds picofarads volts ohms watts
Document #: 38-05392 Rev. *J
Page 13 of 15
[+] Feedback
CY62157DV30 MoBL(R)
Document History Page
Document Title: CY62157DV30 MoBL(R) 8-Mbit (512K x 16) MoBL Static RAM Document Number: 38-05392 REV. ** *A *B *C ECN NO. 126316 131013 133115 211601 Issue Date 05/22/03 11/19/03 01/24/04 See ECN Orig. of Change HRT CBD AJU Description of Change New Data Sheet Minor Change: Change MPN and upload. Change from Preliminary to Final Changed Marketing part number from CY62157DV to CY62157DV30 in the title and in the Ordering Information table Added footnotes 4, 5 and 11 Modified footnote 8 to include ramp time and wait time Removed MAX value for VDR on Data Retention Characteristics table Changed ordering code for Pb-free parts Modified voltage limits in Maximum Ratings section Added 45-ns and 70-ns Speed Bins Added Automotive product information Added test condition for 45 ns part (footnote #13 on page 4) Added Pb-Free Automotive Part in the Ordering Information Removed `Preliminary' tag from Automotive Information Changed the address of Cypress Semiconductor Corporation on Page #1 from "3901 North First Street" to "198 Champion Court" Updated the thermal resistance table Updated the ordering information table and changed the package name column to package diagram Added Automotive-A product Updated ordering Information table Removed 45ns speed bin Removed Auto-A/Auto-E information Removed 48-Pin TSOP I information Updated ordering Information table Updated package diagrams. Removed CY62157DV30LL-70BVXI part related info Updated ISB1/ISB2/ICCDR test conditions to reflect byte power down feature Updated datasheet as per new template Added Acronyms and Units of Measure table Added Ordering Code Definition Updated Package Diagram to 51-85150 *F Converted all tablenotes into footnotes
CBD/LDZ Change from Advance to Preliminary
*D *E *F *G
236628 257349 372074 433838
See ECN See ECN See ECN See ECN
SYT/AJU PCI SYT ZSD
*H *I
488954 2897932
See ECN 03/23/2010
VKN VKN
*J
3068300
10/25/2010
RAME
Document #: 38-05392 Rev. *J
Page 14 of 15
[+] Feedback
CY62157DV30 MoBL(R)
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.
Products
Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch USB Controllers Wireless/RF cypress.com/go/USB cypress.com/go/wireless
PSoC Solutions
psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5
(c) Cypress Semiconductor Corporation, 2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-05392 Rev. *J
Revised October 25, 2010
Page 15 of 15
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.
[+] Feedback

▲Up To Search▲

Price & Availability of CY62157DV3010

	To Download CY62157DV3010 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .